Novel FPGA-Based Signature Match Circuit for Efficient Network Intrusion Detection

This paper introduces a novel FPGA-based signature match co-processor that can serve as the core of a hardware-based network intrusion detection system (NIDS). The key feature of the signature match co-processor is an architecture based on the shift-or algorithm, which employs simple shift registers, or-gates, and ROMs where patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems. Key-Words: Network Intrusion Detection System, FPGA implementation, Pattern Matching